What is MicroBlaze?
MicroBlaze is a soft microprocessor core designed for Xilinx FPGAs.
To get MicroBlaze serial output, you need a UART configured. The fastest way is enabling JTAG UART and see the console messages in debug console (e.g. xsdb).
To leverage FPGA console(e.g. zuestoll01-fpga) you need an UART IP or an iomodule that output UART signals, and connect it to the pins dedicated for FPGA console described in the enzian schematics.
(If you haven't read the quickstart guide, read it!)
How to use MicroBlaze on Enzian FPGAs?
Here we guide you step by step to set up MicroBlaze IP using Vivado and the binary running on MicroBlaze using Vitis, and finally deploying those on Enzian.
This tutorial is a supplement for the youtube video tutorial (below) to make it work on Enzian, and thus is mainly based on GUI of Vivado and Vitis.
Part 1 - Vivado workflow
After creating a brand new project for our hello world example, create a Block Design in Vivado.
Add MicroBlaze IP and Run Block Automation that is suggested by Vivado. For the options, you could choose 64KB local memory, and enable "Interrupt Controller".
Instead of planning a reset pin, you could feed a constant value 1 to the reset to disable external reset:
Configure the console output
We need a way to interact with the soft core, enabling conosle uart is by tradition the way.
There are several ways to get the console output from MicroBlaze:
1. Using the Micaroblaze Debug Module. Check "Enable JTAG UART".
This will enable uart over JTAG and you can see the console output as part of the debug messages in XSDB terminal (more on this).
2. Using UART IP such as AXI UART 16550 or AXI Uartlite
Add an uart ip block, make some connections and interfaces. (TODO: sample project?)
For uart 16550 as is the case in the video however, we need to make some adjustments both in connection and in the constraints file. We will talk about the constraints in the next section.
One possible way to connect uart 16550 is shown below: 
Where we first create 4 interfaces for sin(Rxd) out(Txd) Ctsn. and Rtsn, which are needed for the FPGA console(zuestollxx-fpga);
then Dtrn is directly feeded to Dsrn, Dcdn and Rin is feeded with a constant 1 (using constant IP block) (credit)
3. Using IOModule IP and configure it to output uart signals.
Refer to the design in soft-ECI project here: https://gitlab.inf.ethz.ch/project-openenzian/fpga-stack/applications/soft-eci
The constraints file
In repo: https://gitlab.inf.ethz.ch/project-openenzian/fpga-stack/static-shell you can find all the constraints one need for enzian FPGA.
And you can find schemetics for here: https://zenodo.org/records/6465908 to know how which pins are physically connected (e.g. to FPGA console).
The final setting looks a bit like this:
set_property PACKAGE_PIN AY26 [get_ports {diff_clock_rtl_0_clk_p}]
set_property PACKAGE_PIN AY27 [get_ports {diff_clock_rtl_0_clk_n}]
set_property IOSTANDARD DIFF_SSTL12 [get_ports {diff_clock_rtl_0_clk_p}]
set_property IOSTANDARD DIFF_SSTL12 [get_ports {diff_clock_rtl_0_clk_n}]
set_property IOSTANDARD LVCMOS12 [get_ports ctsn_0]
set_property IOSTANDARD LVCMOS12 [get_ports rtsn_0]
set_property IOSTANDARD LVCMOS12 [get_ports sin_0]
set_property IOSTANDARD LVCMOS12 [get_ports sout_0]
set_property SLEW SLOW [get_ports rtsn_0]
set_property DRIVE 2 [get_ports rtsn_0]
set_property DRIVE 2 [get_ports sout_0]
set_property SLEW SLOW [get_ports sout_0]
set_property PACKAGE_PIN BB25 [get_ports rtsn_0]
set_property PACKAGE_PIN BA25 [get_ports ctsn_0]
set_property PACKAGE_PIN BB27 [get_ports sout_0]
set_property PACKAGE_PIN BB26 [get_ports sin_0]
After that you could generate bitstream and export hardware as described in the video.